Design and Implementation of a Low Power Second Order Sigma-Delta ADC

Sigma-Delta (∑-∆) analog to digital converters are well known for its use in high accuracy wireless communication applications. It is alternative for low power, high resolution (greater than 12 bits) converters, which can be ultimately integrated on digital signal Processor ICs. In this work Over Sampling concept is used to address the problem of power dissipation and noise in ADCs. In this paper a Second order Sigma-Delta Modulator is implemented using CMOS 0.13μm technology using a 1.2 V power supply. Over sampling ratio are 128 with clock frequency of 5 GHz which gives bandwidth of 20 GHz. The total power dissipation of the modulator is 0.87mW. The area occupied by the modulator is 30μm×35μm. Keywords— Analog to Digital Converter, Sigma-Delta, Low Power, Digital to Analog converter, Oversampling, Quantizer, Summer.